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SH-MobileR2

Overview
Design Support

Overview

SH-MobileR2 is intended for use in portable and mobile devices with support for One-Seg terrestrial digital TV broadcasts, such as car navigation systems and personal navigation devices (PNDs). The SH-MobileR2 operates about 1.5 times as fast as the SH-MobileR and delivers functions providing an even higher level of performance.

Key Features

400 MHz high-speed operation and 256 Kbytes secondary memory cache, making it approximately 1.5 times as fast as its predecessor
High-performance Multi-CODEC video processing IP which supports H.264/MPEG-4 AVC (H.264)
Wide variety of on-chip peripheral functions, including 2-D graphics accelerator, USB 2.0 host/function support (high-speed), an ATAPI controller and an SD host controller with high-speed specification support

Specifications

Product name	SH7724 (R8A77240D500BG)	SH7724 (R8A77240B500BB)
Operating temprerature range	-40 to 85 ℃	-20 to 70 ℃
CPU core	SH-4A (with MMU)
Max. operating frequency	500 MHz
Max. processing performance	900 MIPS, 3.5 GFLOPS (at 500 MHz)
Cache memory	Primary cache: 32 Kbytes instruction/32 Kbytes data, separate Secondary cache: 256 Kbytes instruction/data, shared
Media data RAM	128 Kbytes
On-chip RAM	16 Kbyte
External memory	Dedicated controller for DDR2/MobileDDR Connection via 32-bit bus, max. operating frequency: 166.7 MHz	Dedicated controller for MobileDDR Connection via 32-bit bus, max. operating frequency: 166.7 MHz
	Local bus controller Support for connection to ROM, SRAM, PCMCIA, etc., connection via 16-bit or 32-bit bus, max. operating frequency: 83.3 MHz
Main on-chip peripheral functions	Video I/O (camera module direct connection interface) Video image processing functions (color conversion, image enlargement/reduction, filtering) Image blending function VPU5F (H.264,MPEG-4,VC-1) JPU(JPEG encode, decode) Video output unit LCD control with support for 24-bit TFT color LCD panel 2D graphics accelerator Sound processing unit (24-bit dedicated audio DSP) USB2.0 Host/Function controller (with high-speed mode support) x 2 channels ATAPI interface TS interface DMAC x 12 channels FIFO serial interface x 1 channel 32-bit timer unit x 6 channels 32-bit compare-match timer x 1 channel 16-bit timer pulse unit x 4 channels Realtime clock x 1 channel Watchdog timer x 1 channel I²C Bus interface x 1 channel Key scan interface Asynchronous/clock synchonous serial interface X 6 channels IrDA interface (with v1.2a support) MMC4.2-compliant NAND interface SD memory/SDIO card interface X 2 channels Ethernet MAC (10 M/100 Mbps) H-UDI on-chip debug function
Power-down (low-power) modes	Sleep mode Standby mode R-standby mode U-standby mode
Package	449-pin BGA (21 mm x 21 mm、0.8 mm pin pitch)	441-pin POP-compatible BGA (14 mm x 14 mm、0.5 mm pin pitch)

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