V850E2/Sx4-H

Key Features:

Operating voltage: 3.0 to 3.6 V
Max. frequency: 160 MHz
ROM capacities: 1.5/2 MB flash memory
RAM capacities: 96 to 192 KB
Package: 100-pin plastic LQFP (14 x 14), 144-pin plastic LQFP (20 x 20), 176-pin plastic LQFP (24 x 24)
Minimum instruction execution time: 6.25 ns
CPU features:

• System protection feature (SPF)
• Instruction cache: 8 KB/2-way associative (4 KB/way)

Internalmemory

• Code flash: 1 MB/1.5 MB
• Data flash: 32 KB
• CPU RAM: 96 KB/128 KB
• HBUS-RAM: 32 KB
• Backup RAM: 32 KB

External memory interface (MEMC): SDRAM interface, Multiplexed/separate SRAM interface (8/16 bits)
Interrupts:
- Non-maskable interrupts: 3 sources
- Maskable interrupts: 154/177/224 sources
I/O ports: T.B.D.
Timer function:

• 16-bit timer array unit A (TAUA): 1 unit x 16 channels
• 16-bit timer array unit B (TAUB): 1 unit x 0/16 channels
• 32-bit timer array unit J (TAUJ): 1 unit x 4 channels
• Real-time clock (RTCA)calibration: 1 unit
• Window watchdog timer (WDTA): 2 channels
• OS timer (OSTM): 1 channel
• Encoder timer (ENCA): 0/2 channels

Serial interface:

• CAN (FCN): 1/2 channel (64-message buffer)
• UART with LIN mastercontroller LMA (URTE): 5 channels
• CSI (CSIG): 2 channels
• CSI with FIFO (CSIH): 3 channels
• I2C (IICB): 4 channels
• I2S (IISA): 4/6 channels
• PCM interface (PCM): 1/2 channel
• Media local bus (MLB): 1 channel
• IEBus controller (IEBB): 1 channel

Ethernet controller (ETHA): 0/1 unit (supports MII interface)
A/D converter: 10-bit resolution: 4/12/16 channels
DMA controller: 16 channels
Power-on-clear circuit(POC): Yes (M1 products)/No (M2 products)
Clock monitor (CLMA): 3 channels (Can monitor main clock, high-speed internal oscillator, and PLL0)
Data CRC (DCRA): 1 channel
Key interrupt (KR): 0/8 channels
On-chip debug unit (OCD)
Low-voltage indicator (LVI)
DEEPSTOP mode display output (WAKE)
Operating temperature -40°C to +85°C or -40°C to +105°C