The SH7750R is a 32-bit RISC (reduced instruction set computer) microprocessor, featuring object code upward-compatibility with SH-1, SH-2, and SH-3 microcomputers. It includes an instruction cache, an operand cache with a choice of copy-back or write-through mode, and an MMU (memory management unit) with a 64-entry fully-associative unified TLB (translation look aside buffer). The SH7750R has a 16-kbyte instruction cache and a 32-kbyte data cache.
The SH7750R has an on-chip bus state controller (BSC) that allows connection to DRAM and synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions.
- Operating frequency
- CPU Performance
- 430MIPS(Dhystone)/ 240 MHz
- 360MIPS(Dhystone)/ 200 MHz
- Floating Point: 1.7GFLOPS/ 240 MHz
- Large capacity Cache:16kB instruction + 32kB data
- (2way set associative)
- H-UDI, UBC
- Other features
- 64-bit bus interface
- Pin compatible with the SH7750/SH7750S
- Designated 2-way cache, 1.5-2 times more efficient than conventional products due to 2X increase in capacity
- Due to the use of FPU in DSP processing, MP3s (etc.) can be processed
- Car navigation systems, Digital TVs, Image Processing, Digital TVs, Printers, STBs
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