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Product Overview:

This LSI is a microcomputer (MCU) made up of the H8S/2000 CPU with Renesas Electronics's exclusive architecture as its core, and the peripheral functionsrequired to configure a system such as PC server.
The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit generalregisters, and a simple and optimized instruction set for high-speed operation.The H8S/2000 CPU can handle a 16-Mbyte linear address space. The instructionset of the H8S/2000 CPU maintains upward compatibility at the object level withthe H8/300 and H8/300H CPUs. This allows a transition from the H8/300, H8/300L,or H8/300H to the H8S/2000 CPU.
This LSI is equipped with ROM, RAM, two kinds of PWM timers (PWM and PWMX), a16-bit free running timer (FRT), an 8-bit timer (TMR), a watchdog timer (WDT),a serial communication interface (SCI), an I 2 C bus interface(IIC), an LPC interface (LPC), a D/A converter, an A/D converter, and I/O portsas on-chip peripheral modules required for system configuration.
A data transfer controller (DTC) is included as a bus master.
A flash memory version is available,providing the LSI wirh 256, 384, or512-k bytes of ROM. The CPU and ROM are connected to a 16-bit bus,enabling byte data and word data to be accessed in a single state. Thisimproves the instruction fetch and processing speeds.
Two operating modes are provided, offering a choice of address space and singlechip mode/external extended mode. Boot programming into flash memory, on-chipemulation, and boundary scan can be selected as special operating modes.

Key Features:

  • Operating frequency (MHz)/supply voltage (V)
    • 33 MHz/3.0 to 3.6 V
  • On-chip memory
    • ROM: 256kB/384kB/512kB Flash
    • RAM: 40 kB
  • Bus controller
    • Normal bus or multiplexed bus interface
  • LPC: I/O read/write : 3 ch
    • Programmable 16 bit address
    • 64 byte block transfer transmit and receive buffers
  • SCI: 3 ch
    • Smart card I/F support
  • IIC: 6 ch
    • Multi-master/slave function
    • Implements I2C bus extended control register (ICXR)
  • Timer
    • 16 bit free running timer x 1ch
    • 8 bit timer x 4ch (Operation as a 16-bit timer can be performed using TMR_0and TMR_1)
    • Watchdog timer x 2 ch
  • PWM: 14-bit x 4 ch
    • Suitable for fan control
    • Lowest PWM output frequency is 7.9 Hz at 33 MHz
    • Each channel can use a different clock input.
  • CRC
    • Choice 3 polynomial (X8+X2+X+1,X16+X15 +X2+1,X16+X12+X5+1)
  • User debug interface: JTAG interface
  • Package
    Package Code Size Pin pitch
    TQFP-144
    (See Product Lineup.)    		 TFP-144 (PTQP0144LC-A)
    (See Product Lineup.)    		 16.0×16.0 mm 0.4 mm

Key Applications:

Office automation equipment




Built-in Functions

  • High-speed H8S/2000 central processing unit with 16-bit architecture
    • Upward-compatible with H8/300 and H8/300H CPUs on the object level
    • Sixteen 16-bit general registers
    • 65 basic instructions
    • Address space: 16 M bytes
  • Interrupt
    • Internal: 48
    • External: 17
  • Bus controller
    • External data bus width: 8/16 bits
  • Peripheral functions
    • Data transfer controller (DTC) x 85 ch
    • 8-bit PWM timer (PWM) x 16 ch
    • 14-bit PWM timer (PWMX) x 4 ch
    • 16-bit free-running timer (FRT)
    • 8-bit timer (TMR) x 4 ch
    • Watchdog timer (WDT) x 2 ch
    • Asynchronous or clocked synchronous serial communication interface (SCI) x3 ch
    • CRC operation circuit (CRC)
    • I2C bus interface (IIC) x 6 ch
    • LPC interface (LPC) x 3 ch
    • 10-bit A/D converter x 8 ch
    • 8-bit D/A converter x 2 ch
    • Boundary scan (JTAG)
    • Clock pulse generator
  • General I/O ports
    • I/O pins: 106
    • Input-only pins: 9

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