UPD78030x

Key Features:

Operating Voltage : VDD = 2.0 to 5.5 V
Max. frequency : 5 MHz
ROM capacities : 48 KB to 60 KB mask ROM / 60 KB PROM
RAM capacities : 2 KB
Package : 100-pin Plastic LQFP, QFP
Minimum instruction execution time :

• changeable from high speed (0.4 µs: @ 5.0 MHz operation with main systemclock) to ultra-low speed (122 µs: @ 32.768 kHz operation with subsystem clock)

Instruction set suited to system control :

• Bit manipulation possible in all address spaces
• Multiply and divide instructions

Fifty-seven I/O ports (including alternate-function pins for segment signal output)
LCD controller/driver :

• Segment signal output: Max. 40
• Common signal output: Max. 4
• Bias: 1/2, 1/3 bias switching possible

8-bit resolution A/D converter: 8 channels
Serial interface: 3 channels

• 3-wire serial I/O/SBI/2-wire serial I/O/I2C bus mode: 1 channel (µPD780306Y, 780308Y, 78P0308Y)
• 3-wire serial I/O/SBI/2-wire serial I/O mode: 1 channel (µPD780306, 780308, 78P0308)
• 3-wire serial I/O/UART mode: 1 channel
• 3-wire serial I/O mode: 1 channel

Timer: 5 channels

• 16-bit timer/event counter: 1 channel
• 8-bit timer/event counter: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel

Twenty-one vectored interrupt sources
Two test inputs
Two types of on-chip clock oscillators (main system clock and subsystem clock)