Production TechnologyPart 4―How Renesas Handles Semiconductor Finishing

Pursuing high reliability and low cost through the latest packaging technology; SiP solutions that tie in with SoC development are a particular strength.

As an operator of a number of semiconductor finishing plants, Renesas was an early adopter of measures such as lead-frame standardization in pursuit of lower costs and improved package reliability. The ever-increasing demand for smaller and slimmer packages for miniaturized end products is driving the trend toward greater use of SiP (System in Package) solutions. SiPs, which combine a number of chips in a single package, are becoming the norm in many applications, and we are a major supplier of SiPs. We also put a lot of effort into the field of SoC (System on Chip) technology, which is packing greater functionality within the chips themselves.

One of the strengths of Renesas is that we can offer total package solutions based on both SoC and SiP technologies. A key to our success in this area is taking SiP requirements into account during the design of SoC devices. For this article on packaging technology, we discussed the latest developments in the field with Toshihiko Sato, who is Deputy Manager of our Packaging and Testing Technology Department.

"Semiconductor finishing" is the process of encasing the semiconductor chips (hereafter called "die") produced from wafers in packages such as QFPs (Quad Flat Packages), BGAs (Ball Grid Arrays), and CSPs (Chip Scale Packages) (see Figure 1). Moreover, finishing can be broadly divided into two areas: packaging (package assembly) and testing.

Packaging is a multi-step process. Typically it involves receiving the wafers produced in primary production facilities, grinding the rear surface of the wafer down to the required thickness, and cutting the wafer into individual die. Subsequently, it entails placing each die onto a die pad of a lead frame, connecting the leads and die via wires, and encasing the entire assembly in resin. Next, the leads are plated and bent into shape, completing the packaging process.

Testing is a multi-step process, too. At minimum it consists of measuring the electrical characteristics of the semiconductor device using test equipment (testers) and then checking the external appearance of the device either visually or by machine.

Renesas Technology is a leading international semiconductor business, and we derive our strength from the technical aspects of design and production. In other words, the company is an ITDM (Integrated Technology & Device Manufacturer). "Talking about just the area of semiconductor finishing, we operate finishing plants in both Japan and overseas," Mr. Sato explained. "Our Japanese operations generally focus on products with high added value and short delivery times, while our overseas operations typically concentrate on low-cost and high-volume products. Our Japanese plants act as development sites and take on the role of mother fab to the overseas plants. They are also responsible for developing environmentally friendly packaging that is lead-free, halogen-free, and so on."

Renesas is strengthening its Japan-based facilities. This is evidenced by the recent opening of a new building by Renesas Kyushu Semiconductor Corporation in December 2006 (see photograph).

In the past, advances in semiconductor packaging were in areas such as smaller size, higher pin count, and lower cost. Now, the QFP and its derivatives make up the bulk of packages with 200 or fewer external pins. They represent the largest package group in terms of the number of devices shipped. The most important requirement for QFP technology is to lower the production cost. To do this, we looked at various areas, one of which was the lead frame, the part that provides the framework for the device package. Our previous practice was to order lead frames with different specifications to accommodate different die sizes. This customization was determined to be unnecessarily expensive. As a result, we significantly reduced costs ― while also improving reliability ― by standardizing QFP lead frames (see Figure 2).

For devices with more than 200 external pins, the BGA and its derivatives have become the main type of packaging. Of these, a BGA-type package called CSP (Chip-Scale Package) has been miniaturized to the point where the package size is only slightly larger than the die it contains. Package density is commonly represented in terms of the ratio of the die area to the package area (die/package area as a percentage). By this measure, CSPs achieve a ratio of close to 100 percent.

SiP (System in Package) technology has been developed as a way to achieve even greater package density. It satisfies customer requirements for higher levels of miniaturization by mounting a number of chips in a single package. Features of the technology include small size, light weight, slim profile, high reliability, low levels of noise, a high tolerance for external radiation, high speed, and short delivery times.

There are two types of SiPs. In "planar" types, the semiconductor chips are arranged in the same horizontal plane. In "stacked" types, the chips are layered (see Figure 3). Applications that require a high mounting density use stacked-type SiPs.

In principle, a SiP can be made from any combination of semiconductor chips. In practice, however, many SiPs consist of a processor and large-capacity memory. "This combination has great benefits for customers," Mr. Sata said. "It eliminates the need to design the memory bus, thereby shrinking development times and reducing the demands on design resources. Also, because no separate memory chips are required, the customer's supply chain is simplified."

Another benefit that should not be overlooked is that SiP devices typically generate less EMI than designs that use separate ICs, The reason is that the memory bus is a common source of noise. A SiP dramatically shortens the length of the wires between the processor and memory, thereby reducing EMI.

Early generations of SiP devices mostly were produced using existing semiconductor chips. In fact, based on Renesas' experience, in 2000 nearly 90 percent of SiPs used existing chips. Today, though, most SiPs (about 90 percent of them, according to our data) contain newly designed SoCs tailored for the requirements of the specific application(s) that the SiP targets.

Providing optimized SiP solutions to customers is very difficult for companies that are not vertically integrated semiconductor businesses, as Renesas is. "Of course, other companies can produce SiPs using a combination of commercially available chips. However, to produce solutions that offer something a little special, both SoCs and SiPs are required. And it's necessary to develop the SoC and SiP in tandem, in consultation with the customer," Mr. Sato said.

Thus, Renesas has established the capability to design SoCs and SiPs together (see Figure 4). Among other advantages, the coordinated approach we use lets us take account of the wiring between semiconductor chips on the SiP and adjust the location of the terminal pads on the SoC accordingly.

Producing SiPs in volume entails overcoming unique technical challenges (see Figure 5). Solutions must be found for a number of problems. For example, to minimize the height of stacked SiPs, the components are made thinner. But making the wafers, mold resin, and base thinner means that each of these is more prone to bending, which can cause circuit failure. Also, differences in the semiconductor chip dimensions and pad locations can make wire bonding more difficult. "Renesas has developed considerable experience in finding solutions to these and other challenges of miniaturization. Our expertise enables us to mass produce compact SiPs that meet high standards of quality and offer excellent reliability," Mr. Sato stated.